In the fabrication of semiconductor devices and integrated circuits, it is often desirable to electrically isolate one device or portion of a circuit from another. As described in an article entitled "Large High-Density Monolithic XY-Addressable Arrays For Flat-Panel LED Displays" by B. L. Frescura, H. Luechinger, and C. A. Bittmann" in IEEE Trans. Elec. Dev., Vol. ED-24, No. 7, July, 1977, pp. 891-897 ("Frescura et al"), at p. 893, there are four basic isolation structures that are presently used in the prior art for accomplishing this. These isolation structures are referred to as: (1) an air isolation structure; (2) a dielectric isolation structure; (3) a junction isolation structure; and (4) a resistive isolation structure.
Each of these prior art isolation structures suffer from one or more drawbacks. As an example, one drawback of the air isolation structure occurs because a conducting layer is etched through to produce a non-planar semiconductor surface. The resulting non-planar semiconductor surface can make subsequent processing difficult. As another example, one drawback of the dielectric isolation structure is that it often needs to be fabricated by a complicated process which may not be compatible with planar processing. As a result, subsequent processing may be difficult. As yet another example, one drawback of the junction isolation structure is that it cannot be used with non-localized p-n junctions because either the p-type or n-type semiconductor will be of the same type as the diffused area and a continuous conduction path will be formed therethrough. As still yet another example, one drawback of the most common and effective resistive isolation structure, which structure makes the semiconductor resistive by introducing mid-gap states by ion implantation, is that there are limits to the depths that can be reached by ion implantation. As a result, this renders a resistive isolation structure inapplicable in many cases.
As a result, there is a need in the art for an isolation structure and a method of fabrication thereof for use in isolating p-n junctions which is applicable for use with non- localized p-n junctions and which is compatible with planar processing even when the conducting epitaixial layer is relatively thick.
Closely coupled with the need to provide electrical isolation structures is a need in the art to fabricate multiplexed LED arrays. Most previous multiplexed arrays have been fabricated by forming localized p-n junctions by diffusion and by isolating them by means of a junction isolation structure formed by diffusion. Such multiplexed arrays have been disclosed in the Frescura et al article and in an article entitled "Monolithic GaP Green-Emitting LED Matrix-Addressable Arrays" by D. L. Keune, M. G. Craford, W. O. Groves, and A. D. Johnson in IEEE Trans. Elec. Dev., Vol. ED-20, No. 11, November 1973, pp. 1074-1077. The method of forming localized p-n junctions by diffusion limits the class of devices that can be simply processed to homojunctions. On the other hand, while an epitaxially grown p-n junction has many well-recognized desirable features, these advantages cannot be utilized in conjunction with a diffused isolation structure because this method yields full-surface p-n junctions. In order to utilize epitaxially grown p-n junctions in a monolithic circuit requiring electrical isolation, a method must be found to localize the regions of light emission and a structure must be found to electrically isolate the sections of the LED array because, as described above, junction isolation cannot be used to provide electrical isolation of different sections of such an LED array.
One choice of an electrical isolation structure which is compatible with planar processing technology is a resistive isolation structure which is formed by ion implantation. Such a structure is disclosed in an article entitled "Monolithic Matrix-Addressable AlGaAs-GaAs Array" by S. Ray, R. M. Kolbas, M. J. Hafich and B. E. Dies, IEEE Trans. Elec. Dev., Vol. ED-33, No. 6, June 1986, pp. 845-849 ("Ray et al"). However, as discussed above, there are limits to the depths that can be reached by ion implantation. These limits arise, in part, from the difficulty in fabricating implant masks which are thick enough to protect areas which are not intended for implantation and, in part, from limitations on ion energies that are available. These limits, in turn, constrain the design of the device.
Still further, and also closely coupled with the need to provide electrical isolation structures and multiplexed LED arrays, is a need in the art to fabricate multi-color LED arrays. For example, there have been several attempts in the prior art to fabricate two-color LED arrays. One prior method for fabricating two-color LED arrays was disclosed in U.S. Pat. No. 4,198,251. As disclosed in FIG. 1 of the patent, this method relies on doping level to provide a variation in bandgap such that more heavily doped layers, for example, layer 2A in FIG. 1, have a smaller bandgap than more lightly doped layers, for example, layer 2B in FIG. 1. As a result, light emitted in the heavily doped layers will not be absorbed as it travels through more lightly doped layers. Thus, the heavily doped layers are placed beneath more lightly doped layers to increase emission from the LED surface. In this method, a p-n junction is formed by diffusing a p-type dopant species into n-type epitaxially grown layers to the appropriate depth. However, the disclosed method has a drawback which is caused when the diffusion extends through the high bandgap material and into the smaller bandgap material, for example, region 6 in FIG. 1. As a result of this, a p-n junction exists along the edges of the diffused region, not only in the small bandgap material, but also in the higher bandgap material. For this reason, carriers may be injected into both the high and low bandgap materials simultaneously, thereby reducing the efficiency of the intended emission.
Another prior art method for fabricating two-color LED arrays, disclosed in an article entitled "Dual Wavelength Surface Emitting InGaAsP L.E.D.s" by T. P. Lee, C. A. Burrus, and A. G. Dentai in Electron. Lett., Vol. 34, 1980, pp. 401-402, avoids the above-described problem of unintended injection into a higher bandgap material by using a mesa etch to isolate two LED devices. In addition, this method has the further advantage of using epitaxially grown p-n junctions. This is an advantage because epitaxially grown p-n junctions are inherently more efficient than diffused p-n junctions, which diffused p-n junctions are disclosed in the above-described patent. However, because the method disclosed in the article requires non-planar processing, fabrication is difficult and this fact limits the usefulness of the disclosed method in arrays of more than two LEDs.
As a result, there is a need in the art for multiplexed, multi-color LED arrays and a method of fabrication thereof which permits the use of epitaxially grown p-n junctions, which avoids the use of diffused p-n junctions and the resulting unintended injection along the walls of the diffusion, which utilizes an isolation structure which is compatible with planar processing, and which can use a single-level or a double-level metal addressing scheme.